1. Field
Exemplary embodiments of the present invention relate to a non-volatile memory device and a fabrication method thereof, and more particularly, to a non-volatile memory device having a three-dimensional structure where memory cells are formed along the channels perpendicularly protruding from a substrate, and a method for fabricating the non-volatile memory device.
2. Description of the Related Art
Non-volatile memory device retains data although power is turned off. Diverse non-volatile memory devices, such as flash memory devices, are widely used.
A memory device having a two-dimensional structure is formed in a single layer on a silicon substrate and has reached its structural limitation in increasing the integration degree thereof. For alleviating the above concern, a non-volatile memory device having a three-dimensional structure has been suggested. The non-volatile memory device includes a plurality of memory cells stacked along channels and the channels are protruded perpendicularly from a silicon substrate.
FIG. 1 is a cross-sectional view illustrating a conventional non-volatile memory device having a three-dimensional structure.
Referring to FIG. 1, a first conductive layer 12 for forming a gate electrode of a pipe channel transistor is formed over a substrate 11, and a stacked structure, where a second conductive layer 14 for forming the gates of a plurality of memory cells and an inter-layer dielectric layer 13 for isolating or separating each layer of the second conductive layer 14 are alternately stacked, is formed over the first conductive layer 12. The stacked structure, where the inter-layer dielectric layer 13 and the second conductive layer 14 are alternately stacked, is referred to as a cell gate structure CGS hereinafter.
A pair of cell channel holes is disposed inside the cell gate structure CGS by penetrating the cell gate structure CGS, and a pipe channel hole for coupling the cell channel holes of the lower portions is disposed inside the first conductive layer 12. A memory layer 15 is formed on the internal walls of the cell channel holes and the pipe channel hole, and the cell channel holes and the pipe channel hole with the memory layer 15 are filled with a channel layer 16.
As a result, the first conductive layer 12 and a pipe channel transistor formed of the memory layer 15 and the channel layer 16 that are formed inside the pipe channel hole are disposed over the substrate 11. Over the pipe channel transistor, the memory layer 15 and the channel layer 16 are formed inside the pair of the cell channel holes. A plurality of memory cells, that are formed of the second conductive layers 14, are stacked vertically along the memory layer 15 and the channel layer 16 and isolated for each cell channel hole by a slit T. The memory cells isolated for each cell channel hole are serially coupled through the pipe channel transistor disposed under the memory cells so as to form a string.
According to the conventional technology, however, the first conductive layer 12 that is used as a gate electrode of the pipe channel transistor is to be isolated from the second conductive layer 14 that is used as a gate electrode of a memory cell. Therefore, the inter-layer dielectric layer 13 is disposed over the first conductive layer 12.
The presence of the inter-layer dielectric layer 13 allows the first conductive layer 12 to be contacted with the side surface and lower surface of the channel layer 16 that fills the pipe channel hole. In this case, a gate bias applied to the first conductive layer 12 may not adequately supplied to the channel layer 16 that fills the pipe channel hole. In particular, since an inversion layer is not formed in the channel layer 16 in the region (refer to ‘A’) between the first conductive layer 12 and the lowermost second conductive layer 14, on current (Ion) characteristics of the pipe channel transistor may be deteriorated, which leads to poor operation of the non-volatile memory device.